1. Field of the Invention
The present invention relates to a highly integrated semiconductor memory device, and more particularly, to a memory cell of a buried-storage type the size of which is minimized.
2. Description of the Prior Art
In the field of semiconductor devices, it has been attempted to decrease the size of the device as much as possible. For example, in a RAM cell (Random-Access Memory Cell) of a 1-transistor cell type, including one transistor and one storage capacitor, a buried-storage technique was employed for minimization of the cell. In such a buried-storage type 1-transistor RAM cell, the storage capacitor is buried under an epitaxial layer formed on a silicon substrate. Therefore, the capacitor region is not exposed on the surface of the cell and also, the size of the cell is reduced by the size of the capacitor. As a result, as hereinafter described in detail, the area of the device is 8F.sup.2, where "F" represents both the minimum width of a patterning line and the minimum width of the spacing between two adjacent patterning lines The value "F" is determined by the lithography technique. For example, when using optical lithography means, the value "F" is on the order of two micrometers, and when using electron-beam exposure means, the value "F" is on the order of one-half micrometer.
The size of the buried-storage type 1-transistor cell has been further reduced by using a VMOS technique. In the VMOS-type 1-transistor cell, the required size is smaller than 8F.sup.2. However, it is desirable to minimize the size of the 1-transistor cell even further. In addition, it is very difficult to manufacture the VMOS-type 1-transistor cell because of its special structure having a pyramid-shaped hole.
FIG. 1 illustrates a cross-sectional view of a buried-storage type 1-transistor RAM cell 1 of the prior art. In FIG. 1, an N.sup.+ -type buried layer 22 is formed by diffusion at the surface of a P-type silicon semiconductor substrate 10. A P-type epitaxial layer 12 is formed on the N.sup.+ -type buried layer 22 and on the P-type silicon semiconductor substrate 10. Field-oxide regions 24 for isolating the cell 1 from neighboring cells are formed by diffusion into the P-type epitaxial layer 12. An N.sup.+ -type gate electrode 20 is formed through a gate-oxide layer 18, which serves to insulate the gate electrode 20 from the P-type epitaxial layer 12. An N.sup.+ -type drain region 14 and an N.sup.+ -type source region 16 are formed by diffusion at the surface of the P-type epitaxial layer 12 and at both sides of the gate electrode 20. The junction capacitance between the N.sup.+ -type buried layer 22 and the surrounding P-type region of the silicon substrate 10 and the epitaxial layer 12, acts as a charge-storage region. Thus, the buried-storage type 1-transistor RAM cell 1 of FIG. 1 is constructed to include one planar-type transistor and one buried-storage capacitor.
An equivalent circuit diagram of the buried-storage type 1-transistor RAM cell 1 of FIG. 1 is illustrated in FIG. 2, wherein cell 1 comprises a MOS transistor Q and a capacitor C. A gate G, a drain D and a source S of the transistor Q are connected respectively to a word line WL, a bit line BL and one electrode of the capacitor C. The other electrode of the capacitor C is grounded. In operation, when information designated "1" is to be stored in cell 1, the cell is activated by the word line WL and the bit line BL so as to turn on the MOS transistor Q and thus charge capacitor C. When information designated "0" is to be stored in the cell 1, the cell is not activated and no charge is stored in the capacitor C. In order to read out the information stored in the cell 1, gate G is opened and the electric potential of the bit line BL is detected by a sense amplifier. If the information "1" is stored in the cell 1 capacitor C will discharge thus changing the electrical potential detected at bit line BL. If the information "0" is stored in the cell 1, no discharge occurs and the potential is not changed.
FIG. 3 is a plan view of the buried-storage type 1-transistor RAM cell 1 of FIG. 1. The cell 1 is positioned in the center portion of FIG. 3. Cell 1 comprises the N.sup.+ -type drain region 14, the gate electrode 20 and the N.sup.+ -type source region 16 arranged in a series in the transverse direction or horizontal direction as shown in FIG. 3. The gate electrode 20 is connected to the word line WL extending in the longitudinal direction or vertical direction as shown in FIG. 3. On the periphery of the cell 1, neighboring cells 2, 3, 4, and 5 are positioned around cell 1. Cells 1, 2, 3, 4 and 5 are isolated from each other by the field-oxide regions 24 (hatched areas in FIG. 3), which serve as isolation regions.
The drain region 14, the gate electrode 20 and the source region 16 each has a square shape with a side length of "F". The value "F" is both the minimum width of a patterning line and the minimum width of the spacing between two adjacent patterning lines. Therefore, the size of cell 1 is 1F in the longitudinal direction and 3F in the transverse direction. The distance between the cell 1 and each of the neighboring cells 2 through 5 is also "F". As a result, taking into account the field-oxide regions 24, the size of the surface area for the cell 1 is 4F in the transverse direction and 2F in the longitudinal direction. Consequently, the surface area required by one cell of FIG. 3 is 8F.sup.2.
The surface area of 8F.sup.2 is also required by a memory cell of a charge-pumping type in FIG. 4. FIG. 4 illustrates a cross-sectional view of a charge-pumping type memory cell of the prior art. In FIG. 4, a P-type silicon substrate 10 is formed as an island in a floating state on a sapphire substrate 11. A gate-oxide layer 18 is formed on the P-type silicon substrate 10. An N.sup.+ -type gate electrode 20 is formed on the gate-oxide layer 18. An N.sup.+ -type drain region 14 and an N.sup.+ -type source region 16 are formed adjacent the silicon substrate 10. Thus, an N-channel type MOS FET having a so-called SOS (Silicon-On-Sapphire) structure is constructed.
In order to store information designated "1" in this SOS-type MOS FET, a well-known charge pumping from the inverstion layer into the channel region 10 is effected. The information designated "1" or "0" stored in a SOS-type MOS FET can be determined by detecting a current conducted between the N.sup.+ -type drain region 14 and the N.sup.+ -type source region 16 when a voltage is applied between them. In order to erase the stored information, a well-known avalanche breakdown is effected at the N.sup.+ -type drain region 14 by applying a high voltage of, for example, 9 V to the N.sup.+ -type drain region 14. These charge-pumping type memory devices are described in more detail in U.S. Pat. No. 4,250,569, issued on Feb. 10, 1981, and in IEEE Transaction on Electron Devices Vol ED-16 No. 3, March 1969 "Charge Pumping in MOS Devices".
As mentioned before, the surface area of this SOS-type MOS FET is also 8F.sup.2. Accordingly, the plan view of the SOS-type MOS FET can also be illustrated as in FIG. 3.
In order to realize a large scale integrated memory, it is required that the size of a memory cell be as small as possible.